SUMMARY OF ACTIVITIES
- Expert Witness on PLLs at the International Trade Commission
- Ultra-Wide Band Radio Frequency integrated circuits in SiGe process.
- Optical Phase Locked Loops for Darpa proposal
- Phase noise reduction in SOI Fractional-N Sigma Delta Synthesizer
- Silicon-photonics Mach-Zehnder modulator in SiGe process.
- High speed VCOs in 120GHz and 200GHz SiGe process. Octave-tuning VCO and synthesizer of broad frequency applications.
Numerous other chips include 40G dividers, TIA, Laser driver, TWA, Limiting Amplifier, LNA, Mixer, IQ modulator, VCO's up to 45GHz, and 15 GHz accumulators.
CDR functions in 0.25um through 0.13um CMOS for fiber communications at 2.5Gb/s and 10Gb/s. VCO design and architectures for PLL and data recovery.
Design, layout and test of many integrated circuits for RF in BICMOS on SOI.
2.5 GHz PLL/CRU, and mux/demux functions up to 5 GHz, using 13 GHz bipolar process. Delay Locked Loop (DLL) ICs that had resolution better than 100 pS. MSI circuit for timing delay adjustment, having a resolution of 40 pS.
ATE products in ATT CBICU complementary bipolar process. 275 MHz monolithic PLL and Bipolar RAMDAC.
Combination A/D and D/A converter for sub-ranging hybrid product. Sample-hold, current mode amplification and characterization of both ADC and DAC. 75 MHz reduced power 8-bit A/D converter IC.
Monolithic Microwave Integrated Circuit (MMIC) 6-to-18 GHz amplifiers in GaAs, including hybrid. S-parameter modeling of transistors.
Ten patents and published numerous articles in the area of mixed signal design.
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